The use of silicon on insulator (SOI) substrates in the fabrication of integrated circuit devices is well known in the art. With reference to FIG. 1, an SOI substrate 10 typically comprises a semiconductor bulk handle wafer 12, an insulating layer 14 and a semiconductor film 16 arranged in a stack. The semiconductor film 16 may be doped in accordance with the application, or alternatively may be un-doped in which case the SOI substrate 10 is of the “fully-depleted” type. The semiconductor film 16 may, for example, have a thickness of 35-70 nm. The insulating layer 14 is commonly referred to in the art as a buried oxide (BOX) layer.
It is common for certain integrated circuit devices, such as those used in imaging where the semiconductor film 16 is fabricated to include a photosensitive region, for epitaxial growth processing to be used to increase the thickness of the semiconductor film. For example, a thick semiconductor film 18 with a thickness of 2-20 μm is not uncommon. An example of such a thick SOI substrate 10′ is shown in FIG. 2 with the thick semiconductor film 18 including the epitaxial portion 16′ over the semiconductor film 16. The epitaxial portion 16′ may be doped in accordance with the application.
In a number of circuit applications, it is necessary to effectuate voltage control over the biasing of the semiconductor bulk handle wafer 12. FIG. 3 illustrates one known method and structure for making an electrical contact to the semiconductor bulk handle wafer 12. In this implementation, a deep etch is made from the front surface of the thick semiconductor film 18, with the deep etch extending through the epitaxial portion 16′, the semiconductor film 16 and the insulating layer 14 and further partially extending into the semiconductor bulk handle wafer 12. The opening formed by the deep etch is lined with a barrier liner 20 and filled with a metal fill 22. The barrier liner 20 may, for example, comprise a Titanium or Tantalum Nitride material and the metal fill 22 may, for example, comprise a copper material to form a conductive bulk contact 24. The material of the barrier liner 22 is selected to prevent contamination of the semiconductor material by the metal fill 22. Deep trench isolation (DTI) structures 26 may be formed to surround the bulk contact 24 so as to isolate the region 28 of the thick semiconductor film 18 where the bulk contact 24 is formed from the active region 30 of the thick semiconductor film 18 where integrated circuit structures are fabricated. The process for forming the DTI structures 26 utilizes a deep etch that is made from the front surface of the thick semiconductor film 18, with the deep etch extending through the epitaxial portion 16′ and the semiconductor film 16 and further partially extending into the insulating layer 14. The opening formed by this deep etch is then filled with an insulating material.
FIG. 4 illustrates another known method for making an electrical contact to the semiconductor bulk handle wafer 12. In this implementation, a deep etch is made from the front surface of the thick semiconductor film 18 extending through the epitaxial portion 16′, the semiconductor film 16 and the insulating layer 14 and partially extending into the semiconductor bulk handle wafer 12. The opening formed by the deep etch is then filled with a metal plug 32. The metal plug 32 may, for example, comprise tungsten material to form a bulk contact 34. Deep trench isolation (DTI) structures 26 may be formed to surround the bulk contact 34 so as to isolate the region 28 of the thick semiconductor film 18 where the bulk contact 34 is formed from the active region 30 of the thick semiconductor film 18 where integrated circuit structures are fabricated. The process for forming the DTI structures 26 utilizes a deep etch that is made from the front surface of the thick semiconductor film 18, with the deep etch extending through the epitaxial portion 16′ and the semiconductor film 16 and further partially extending into the insulating layer 14. The opening formed by this deep etch is then filled with an insulating material.
The bulk contacts and methods of making described above suffer from a number of drawbacks including: a need to use a thick resist or hard mask to make the deep etch; a need to control surface flatness of the thick semiconductor film 18; a need to avoid contamination of the thick semiconductor film 18; thermal budget limitations that affect process steps; a challenging aspect ratio for the deep etch; and possible introduction of undesired stress.
There is accordingly a need in the art to provide an improved process for forming a contact to the semiconductor bulk handle wafer of an SOI substrate.